Overview
The GEMM kernel computesC = A * B where:
- Matrix A is MxKxL (L is batch dimension)
- Matrix B is NxKxL
- Matrix C is MxNxL
- Utilizes GPU tensor cores for MMA operations
- Multi-stage pipelining to overlap compute and memory access
- Shared memory buffering for efficient data transfer
- Support for various data types (fp16, bf16, fp8, int8, tf32)
Ampere Architecture Example
Blackwell Architecture Example
For Blackwell GPUs, the implementation uses more advanced features:Key Blackwell Features
Tensor Memory Access (TMA) TMA provides efficient memory operations:Running the Example
Performance Profiling
Use NVIDIA Nsight Compute to profile your kernel:Key Concepts
Tile Shape Selection
Tile Shape Selection
The tile shape determines how the problem is divided:
- M dimension: Affects register usage and occupancy
- N dimension: Should align with MMA instruction shape
- K dimension: Larger values improve arithmetic intensity
- Ampere: 128x128x32, 128x256x32, 256x128x32
- Blackwell: 128x128x64, 256x128x128
Memory Hierarchy
Memory Hierarchy
Understanding the memory hierarchy is crucial:
- Global Memory (GMEM): Input matrices A, B, output C
- Shared Memory (SMEM): Tile-level cache, swizzled to avoid bank conflicts
- Registers (RMEM): Thread-level storage for MMA operands
- Tensor Memory (TMEM): Blackwell-specific accumulator storage
Pipeline Stages
Pipeline Stages
Multi-stage pipelining overlaps memory and compute:
- Stage 1: Load next tile from GMEM to SMEM
- Stage 2: Compute current tile MMA
- Stage 3: Write previous results to GMEM
Source Code
Ampere GEMM
Complete source:
examples/python/CuTeDSL/ampere/tensorop_gemm.pyBlackwell GEMM
Complete source:
examples/python/CuTeDSL/blackwell/dense_gemm.py